标 题: IBM ASIC design center recruitment
发信站: 日月光华 (2008年08月01日16:41:37 星期五), 站内信件

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ASIC application engineer requirement
Job Scopes & Responsibilities:
IBM ASIC/back-end design engineer is resposible for physical implementation
of very large scale CMOS SoC/ASIC design from netlist handover to GDS
tapeout, based on IBM 90nm, 65nm, 45nm and beyond technology with
IBM/industry leading EDA tools. The work scope includes one or more of
following areas:
- Supporting customer on IBM IP core usage, IO selection and netlist
preparation/synthesis.
- Working with customer to define physical implementation strategies
including logic partition, design planning, etc.
- Top level insertion and netlist processing, including IO
assignment/insertion, JTAG structure building, scan chain & BIST insertion,
etc.
- Timing assertions/constraints specification and verification, STA
analysis and design timing closure;
- Physical design, floorplanning, I/O planning, physical synthesis, clock
tree generation and tuning, place &route;
- Physical verification and reliability verification;
- ASIC package design, image(power bus) creating and verification
- On chip and package power bus analysis, chip and system cominbational
SI/PI analysis.
- Design signoff
- Coordinating with other IBM function teams to support the related problem
solving during SoC/ASIC design execution.
The candidate would also have future extended responsibility participating
in the design planning and sizing for the advanced ASIC/SoC chips, and
development, deployment and other application engineering support of the
design methodology.

Job Requirements:
1. CS/EE related background in digital chip design areas
2. Industry experience (1-2 years as entry level, more is preferable) in
CMOS SoC/ASIC physical architecture implementation ("back-end" design)
3. Proficient with relevant EDA tools/flows such as Synopsys, Cadence and
Mentor, etc. Experience in IBM ASIC tools/flow will be a significant plus.
4. Solid knowledge and industry experience in one or more of the following
areas:
- Design floorplanning and partitioning
- Logic synthesis, design for test, and I/O assignment
- High level clock design, clocking and routing optimization
- Timing/Signal integrity analysis and closure
- Physical synthesis, place and route, physical design optimization
- Physical extraction, verification and reliability verification
- Package/system design, SI/PI analysis
- Multiple layer(4+) PCB layout, Cadence layout/SI tool and Hspice
- ASIC design release/signoff
5. Good communication skill in both English and Mandarin.
6. Strong teamwork sense, and self-motivation is required.
7. Strong technical leadership will be important consideration for senior
positions
English: Fluent

If you have interest , pls mail to:

lcdlwei@gmail.com


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※ 来源:·日月光华 bbs.fudan.edu.cn·[FROM：nu le]