发信人: windy (风铃~~我想家), 信区: Job_Post
标 题: 芯原股份有限公司招聘
发信站: 我爱南开站 (2007年11月08日23:05:04 星期四)

我们将于2007年11月14日下午2：00在南开大学东方艺术系举办现场招聘会，欢迎相关专
业的同学届时参加。

芯原股份有限公司(VeriSilicon)成立于2001年，是一家发展迅速的硅产品解决方案公
司，公司提供的产品和服务使客户能够达到他们芯片设计的目标，加速开发项目并以较
低的成本及时提供市场公认的硅产品。
芯原在全球拥有150多个高级工程师和设计中心，客户能够真正利用全球设计服务公司为
他们的硅项目提供支持并实现设计和成本目标。芯原在加州圣塔克拉拉、德州达拉斯、
中国上海北京、中国台湾台北、日本东京、法国尼斯和韩国首尔拥有设计、经营和销售
支持办事处。

2005年，芯原排名德勤中国高科技、高成长50强 (Deloitte Technology Fast 50
China) 第三名以及德勤亚太区高科技高成长500强 (Deloitte Technology Fast 500
Asia Pacific) 第六名。芯原还荣获 Red Herring 亚洲尚未上市企业100强企业 (Red
Herrings 100 Private Companies of Asia) 之一，并入选 EE Times 全球60家最具潜
力半导体初创公司 (EE Times 60 Emerging Startups)。

1. Analog Circuit Design Engineer
模拟电路设计工程师
Responsibilities:
 Devise and develop deep sub-micron CMOS analog circuit
设计开发CMOS 深亚微米模拟电路
 Guide and/or supervise layout
指导、监督版图设计
 Assist in the design of test boards so as to debug and verify test
chips
协助设计测试板, 调试验证测试芯片
Requirements:
 MS/PHD degree, majored in EE
电子工程专业硕士/博士学历
 Course knowledge and project experience in the related areas
相关课程知识及项目经验
 Good understanding about one of the following disciplines: low
voltage／low noise OPA, ADC & DAC, PLL/DLL, high speed IO, RF and other
analog blocks
熟悉以下单项或多项设计概念：低电压、低噪音OPA；ADC&DAC；PLL/DLL；高速IO；RF和
其它模拟电路
 Self motivated, good communication and team work skills are a must
富有事业心和团队合作精神，沟通表达能力良好


2. Physical Layout/QA Engineer
物理版图设计/质量保证工程师
Job Descriptions:
 Design the layout of deep sub-micron CMOS circuits;
设计CMOS 深亚微米电路版图
 Develop the layout of standard logic cells, memory and IO cells;
开发标准逻辑单元、存储器及输入输出单元版图
 Devise the layout of analog block, memory and High-speed IO cells;
设计模拟电路、存储器和高速IO单元版图
 Conduct layout physical verification.
实施版图物理验证
Requirements:
 BE majored in EE, CS, Physics, Automation or relevant discipline;
电子工程、计算机、物理、自动化或相关专业本科学历
 Course knowledge in at least one of the following areas is
required: Analog block, Memory and High-speed IO layout; training
experience/certificate on layout is preferred;
具备模拟电路, 存储器或高速IO版图方面一门以上课程知识，有版图培训经历或证书者
优先
 Familiar with design rules in deep submicron processing;
熟悉深亚微米工艺设计规则
 Skills in DRC/LVS debugging;
有DRC/LVS 查错技能
 Self motivated, good communication and team work skills are a must.
富有事业心和团队合作精神，沟通表达能力良好


3. Design Implementation Engineer
设计实现工程师
Job responsibilities:
 Logic synthesis and timing analysis
逻辑综合以及时序分析
 DFT (design-for-test) and ATPG
测试电路设计及自动测试向量生成
 Deep sub-micron chip floor plan
CMOS 深亚微米芯片平面布局
 CTS, Power plan, Placement & Routing, and SDF
CTS, 电源方案, 布局布线以及SDF
 Whole chip DRC/LVS
芯片级 DRC/LVS
Requirements:
 Master’s degree or above, majored in EE, CS, Physics or relevant
discipline
电子工程，计算机科学或物理学等相关专业硕士或更高学历
 Course knowledge about logic synthesis, DFT, STA, noise and
crosstalk analysis, physical design, EDA tool and tape-out issue is a must,
project experience in one of the above fields is required
具备逻辑综合，测试电路设计，静态时序分析，噪声及串扰分析，物理版图设计、EDA
工具以及流片课程知识，有部分相关项目经验
 Self motivated, good communication and team work skills, steady
and surefooted work attitude are highly wanted
富有事业心和团队合作精神，沟通表达能力良好, 工作踏实稳定



4. SOC Design Engineer
芯片系统设计工程师
Responsibilities:
 Capable of independently contributing to and working on designs of
ASIC components/modules in terms of RTL coding, logic synthesis, STA and DFT
considerations
胜任RTL代码，逻辑综合，STA和DFT方面ASIC元器件和模块的设计工作，能够独立完成任
务
 Work closely with verification team, physical design, test and
FPGA engineers to solve functional verification, floor-plan, timing and test
issues
密切配合验证工程师、版图工程师、测试工程师以及FPGA工程师，解决功能性验证、平
面版图、时序及测试等方面的问题。
 Be responsible for micro-architecture and implementations of ASIC
functions all the way to chip-level formal verification, timing analysis and
bridge to physical design
负责从微结构、ASIC功能实现、芯片级正式验证乃至时序分析之整个过程，搭建通向物
理设计的桥梁。
Requirements:
 MS/PhD, with at least 1+ years of experience in ASIC design,
including course projects
硕士/博士学历，至少一年ASIC设计经验，包括课程项目
 Possessing the independent mastery of EDA tools and capability of
solving technical issues in one of the following areas is a must：
Synopsys and/or Cadence tools; design specification bring-up, RTL coding and
style critique, chip-level synthesis, static timing analysis, formal
verification and scan-chain insertion
熟练应用EDA工具，能够独立解决至少一项下述领域中的技术问题：
Synopsys 或Cadence 工具；设计规格的制定；RTL代码和格式的审查；芯片级集成；静
态时序分析；验证和扫描链嵌入
 Solid knowledge and proven track record in design flow and
methodologies for deep submicron ASIC development is a plus
在深亚ASIC开发设计流程和方法上有着丰富知识及成功经验者优先
 Strong understanding of ASIC design issues and considerations
relating to silicon success
熟谙ASIC设计中的问题及硅验证事项
 Self motivated, good communication and team work skills are a must
富有事业心和团队合作精神，沟通表达能力良好


5. System Application Engineer
系统应用工程师
Job Descriptions:
 Design and develop various applications for IC products, including
arrangement and debug of hardware on board level, and development of
firmware (like BSP, Driver, API, etc.)
IC产品的应用设计开发，包括板级的硬件设计，调试，相关固件firmware（如RTOS的
BSP，driver, API等等）的开发
 Conduct FPGA verification of SOC, IC and IP circuits
SOC,IC和IP的FPGA验证工作
 Carry out in-house tests for IC products and SOC systems developed
by the company
IC和SOC的实验室测试工作
 Provide technical support for customers regarding product
applications
为客户提供本公司产品的应用技术支持
Requirements:
 Master’s degree, majored in CS, EE or Automation
计算机、电子工程或自动控制专业硕士
 Good programming skills in C and assembly languages
有良好的C语言和汇编语言的编程能力
 Understand ARM architecture and its peripheral systems,
understanding of ZSP(a type of DSP) is a plus
熟悉ARM体系及其外部系统, 熟悉ZSP(一种DSP)尤佳
 Good knowledge about FPGA application, Verilog or VHDL hardware
language. Internship or project experience in FPGA synthesis and reuse is
preferred
熟悉FPGA的应用，了解VHDL或Verilog 硬件描述语言。有FPGA综合和设计复用方面的实
习或项目经验者优先
 Good knowledge about Embedded Operating System, for example,
development of embedded LINUX and its driver.
熟悉嵌入式操作系统，如嵌入式Linux及其驱动程序的开发
 Self motivated, good communication and team work skills are a must
富有事业心和团队合作精神，沟通表达能力良好



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Gone with

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人的价值，在遭受诱惑的一瞬间被决定。